PDF) Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata
PDF) Memory testing with a RISC microcontroller
Steffen Tarnick's research works | Universität Potsdam, Potsdam and other places
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PDF) Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique
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PDF) Efficient Test Compaction for Pseudo-Random Testing
Dimitris Magos's research works | University of West Attica, Athens (TEIATH) and other places
PDF) UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations
PDF) Extending Internet into Space – ESA DTN Testbed Implementation and Evaluation
PDF) Modeling and Simulation of Efficient March Algorithm for Memory Testing
PDF) An adaptive BIST to detect multiple stuck-open faults in CMOS circuits
PDF) Survival analysis for modeling critical events that communities may undergo in dynamic social networks
PDF) Detection of Delay Faults in Memory Address Decoders
PDF) Delay-Insensitive Cell Matrix.
PDF) A domain-specific approach for software development on Manycore platforms
PDF) Accumulator-Based Weighted Pattern Generation.
PDF) Symmetry Measure for Memory Test and Its Application in BIST Optimization
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead
PDF) Test Embedding with Discrete Logarithms
PDF) Detection of Delay Faults in Memory Address Decoders
